V2U3X4-PCIE4XE103
Quad channel 16-port (4-port x 4) USB 3.0 to PCI Express x4 Gen 2 Host Card
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V2U3X4-PCIE4XE103
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The V2U3X4-PCIE4XE112 is an Quad channel 16-port (4-port x 4) USB 3.0 to PCI Express x4 Gen 2 Host Card. V2U3X4-PCIE4XE112 is integrated by the following three key parts (V2IP4X-PCIE4XG201,V2DU3X2-IPCIE2XG211, V2CB-00592).
Utilizing the standard PCI Express Switch, the 8-Lane/8-Port PCI Express Switch provides the most efficient fan-out solution for integrating Quad PCI Express to USB 3.0 Single Chip Host controllers into a small board design. Each USB 3.0 to PCI Express Single Chip Host controller takes advantages of 5 Gbps burst rate of 4-lane PCI Express bus in both directions and is fully compliant with PCI Express Base specification r2.0. This solution provides full PCI Express and USB 3.0 functionality and performance. |
The Highlight Features
- 5.25″ ODD Form Factor
- Host Bus: PCIe x4 Gen 2 (20.0 Gb/s)
- Compliant with PCI Express Base Specification Revision 2.0
- Quad independent USB 3.0 Host Controllers
- Compliant with Universal Serial Bus 3.0 specification Revision 1.0
- Compliant with Intel’s eXtensible Host Controller Interface (xHCI) specification Revision 1.0
- USB 3.0 Host Controller supports four downstream ports
- Sixteen USB 3.0 Cable Ports (A-type Receptacle, USB IF TID 360000055)
- Provides USB 3.0 cable port lock mechanism
USB 3.0 Standard A-type lock mechanism
| Model | V2U3X4-PCIE4XE103 |
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| Upstream PCIe interface | 4-lane PCI Express Throughput : PCIe Gen 1: 10 Gbps : PCIe Gen 2: 20 Gbps |
| Downstream PCIe interface | Two IOI Proprietary Dual-lane Internal PCIe Ports (PCIe-1~2) : 10X2_19pin Header (Pitch=2.0mm) : 2-Lane PCIe (Two PCIe x1) Throughput of each lane :PCIe Gen 2: 5 Gbps |
| Key Features | Standards Compliant : PCI Express Base Specification r2.0 (Backwards compatible with PCIe r1.0a/1.1) :PCI Power Management Spec r1.2 :Microsoft Vista Compliant :Supports Access Control Services :Dynamic link-width control :Dynamic SerDes Speed Control High Performance :Non-blocking internal architecture :Full line rate on all ports :Cut-Thru latency: 140ns for Link widths of x4 to x1 :Maximum Payload Size - 2,048 bytes :Read Pacing (intelligent bandwidth allocation) :Dual Cast :Dynamic Buffer Pool Architecture for faster credit updates PCI Express Power Management :Link power management states: L0, L0s, L1, L2/L3 Ready, and L3 (with Vaux not supported) :Device power management states: D0 and D3hot :Active State Power Management (ASPM) Quality of Service (QoS) :Two Virtual Channels (VC) per port :Eight Traffic Classes per port :Weighted Round-Robin Port & VC Arbitration |
| Lane Status LEDs Blink: Gen 1 speed Solid: Gen 2 speed | Upstream Lane Status LEDs : LED-Lane0: Upstream x1 Status LED : LED-Lane3: Upstream x4 Status LED |
| Computer Platform Requirements | Desktop computer equipped with a PCIe 2.0/3.0 x4, x8, x16 slot |
| Physical Dimensions | 64.5(H)x81(L)mm NW: 48.5g |
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* Specifications subject to change without prior notice |
